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Features
* * * * * * * * * *
Three DSPs and 24-bit Audio Router On-chip 32 kHz to 96 kHz Sampling Rate 16-bit Microcontroller On-chip Variety of I/Os, including SmartMediaTM and DataFlash (R) Embedded RAM for Single Chip Operation (530 kbit) Warm Start Power-down 1 A Typical Deep Power-down, 0.5 mW/MIPS Typical Operating External Flash/ROM Capability Available in a 64-lead TQFP Package Ideal for Real-time Audio Applications - MP3 Decoding Wavetable Synthesis (GM-Lite) - Effect Processing (Reverb, Echo, Chorus, etc.) - Speech Recognition and Synthesis - Filtering, Sampling Rate Conversion * Typical Applications: Cellular Phones, MP3 Player, Effect Devices, Intelligent Answering Machinces, Toys
Audio Processing ATSAM3103 Versatile Low-power Audio DSP/ Low-cost Effects DSP
Description
The ATSAM3103 is a member of the new ATSAM3000 family that uses DSP Array Technology. The ATSAM3103 includes three 24-bit DSPs, a 24-bit Audio Router and a general purpose 16-bit on-chip CISC Microcontroller. Its high performance and flexibility with eight input and eight output channels allow implementation of professional quality audio applications such as effects processing and MP3 decoding. A variety of I/Os, including SmartMediaTM and DataFlash(R) are provided. Sampling rates up to 96 kHz at 24 bits are supported.
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DSP Array Block Diagram
Figure 1. ATSAM3103 DSP Array Block Diagram
DSP Array (3 P24 DSPs) Embedded RAM 16K x 24
MMU
Sync Bus
Async Bus
16-bit Processor (P16)
I/Os Timers, UARTs, DataFlash, Ports
ROUTER Final ACC MIX Audio OUT Audio IN
Audio I/O
Embedded ROM 1K x 16 BIOS and Debug
External I/O
Functional Description
DSP Array
The ATSAM3103 includes three on-chip DSPs. Each DSP (P24) is built around a 2K x 24 RAM and a 1K x 24 ROM. The RAM contains both data and P24 instructions; the ROM contains typical coefficients such as FFT cosines and windowing. A P24 sends and receives audio samples through the Sync Bus. It can request external data such as compressed audio through the Async Bus. Each P24 RAM can be accessed through the Async Bus. Each P24 is capable of typical MAC operation loops, including auto-indexing, bit reverse and butterfly (multiplication of complex numbers). It also includes specialized audio instructions such as state variable IIR filtering, envelope generation, linear interpolation and wavetable loop. One P24 is sufficient for processing one channel of MP3, implementing a multi-tap delay line or a multi-tap transversal filter. A single P24 is also capable of generating 12 voices of wavetable sound at 32 kHz sampling rate (8 voices at 48 kHz), including sample cache, pitch control, second-order filter and two envelope generators.
Sync Bus
The Sync Bus transfers data on a frame basis, typical frame rates being 32, 44.1, 48 or 96 kHz. Each frame is divided into 64 time slots. Each slot is divided into 4 bus cycles. Each P24 is assigned a hardwired time slot (8 to 63), during which it may provide 24-bit data to the bus (up to 4 data samples). Each P24 can read data on the bus at any time,
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allowing inter P24 communication at the current sampling rate. Slots 0 to 7 are reserved for a specific router DSP, which also handles audio out, audio in, and remix send.
Async Bus
The Async Bus is 24-bit data inside the chip and 16-bit outside. The P16 processor normally masters the Async Bus; it can read/write the P24 memories and the external or embedded ROM/RAM. However, each P24 can request a bus master cycle for accessing external ROM/RAM or other P24 memories. This allows efficient intercommunication between several P24s on asynchronous block basis. Specific P24 instructions FLOAT and FIX convert fixed-point DSP data to floating-point 16 bits. This allows for 20-bit audio dynamic range when using 16-bit external memory.
16-bit Processor
The P16 processor is widely used in ATSAM products. Using the P16 allows to keep the large firmware investments from the ATSAM97xx series. A built-in ROM, connected to the P16, holds basic input/output software (BIOS) for peripherals such as UART, DataFlash, SmartMedia, MPU, as well as a debugger using a dedicated asynchronous serial line. The firmware can reside on external parallel ROM/Flash or it can be downloaded at power-up into the built-in 16K x 24 RAM from serial EEPROM, DataFlash, SmartMedia or host. The MMU handles transfer requests between the external or embedded RAM/ROM, the P16 and the P24s through the Async Bus. The ATSAM3103 includes an on-chip 16K x 24 RAM. This block includes a RAM, accessed through the Async Bus, which defines the routing from the Sync Bus to/from the Audio I/O or back to the Sync Bus (mix send). It takes care of mix and accumulation from Sync Bus samples. Eight channels of audio in and eight channels of audio out are provided (4 stereo in/out, I2S format). The stereo audio in channels may have a different sampling rate than the audio out channels. In this case, one or more P24s take care of sampling rate conversion. The ATSAM3103 includes versatile I/Os that share common pins for reduced pin count and small IC footprint. Most I/Os, when not used for a specific function, remain available as firmware controlled general-purpose pins. The following peripherals are included on-chip: * * * * * * * * 2 x 8-bit timers 2 x 16-bit timers Parallel slave 8-bit port, MPU401 compatible Parallel master 8-bit port, for connection to SmartMedia and/or LCD display, switches, etc. 2 x asynchronous bi-directional serial ports Synchronous serial slave port (SPI type host connection) SPI master bi-directional port for EEPROM or DataFlash connection Firmware controlled I/O pins
MMU (Memory Management Unit) Router: Final ACC, MIX, Audio Out, Audio In
I/O
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Typical Application Examples
Figure 2. Host-controlled MP3 Player
ROM
Compressed Audio (from Host)
ATSAM3103 DAC
Stereo Audio Out
* *
ATSAM3103 firmware download from host (when using parallel interface) Choice of host communication interfaces - - - 8-bit parallel Asynchronous serial(1) Synchronous serial (SPI) (1)
* * *
Full MP3 support inculding very low bit rate extension (ISO/IEC 13813-3) Easily upgradeable to other coding standards Single CBGA on request
1. External firmware serial EEPROM required
Note:
Figure 3. Stand-alone MP3 Player (SmartMedia Based)
8-Mb to 12-Mb Smart Media
Switches, LCD Display MIDI
ATSAM3103 DAC
Stereo Audio Out
* *
S/Pdif connection possible PC connection possible
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Figure 4. Low-cost High-quality Effect
Atmel EEPROM
Switches LCD Display MIDI
ATSAM3103 ADC DAC
Stereo Audio In/Out
* *
High quality, full 24-bit Multi-effects such as reverb, chorus and compression Stereo 10-band graphic equalizer
Figure 5. Intelligent Answering Machines (DataFlash-based)
Atmel DataFlash
Switches LCD Display
ATSAM3103 ADC DAC
Audio In/Out
* * * *
High quality telephone recording at low bit rate (8 kbit/sec) Close to one hour recording capacity using 32-Mbit DataFlash Detects touch-tone Easy to program
Figure 6. Toys with Artificial Intelligence
Atmel EEPROM
Switches Motor ControI
ATSAM3103 ADC DAC
Audio In/Out
* * *
Speech recognition Learning functions ADPCM record/play
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DSP Capacity and I/O Configuration
DSP Considerations
The ATSAM3103 includes three P24 DSPs. Table 1 lists the performance levels achievable by the P24. Table 1. P24 Performance Levels
Function MP3 decode Stereo reverb and chorus @48 kHz 31-band equalizer @96 kHz Stereo 31-band equalizer @48 kHz 256 points FFT or IFFT @96 kHz incl. windowing P24s Required 3 1 3 3 1
The ATSAM3103 runs firmware from built-in 16 x 24 RAM. The firmware should be downloaded at power-up. This can be done from the following: * * * * A small 256-kbit external EEPROM with SPI interface such as the Atmel AT25256 A DataFlash (current capacities range from 1 Mbit to 64 Mbits) if audio storage functions are required A SmartMedia card (supported capacities from 8 Mbytes to 128 Mbytes) Parallel MPU type interface
I/O Selection Considerations
Host-controlled Operation
I/Os are organized in groups that can be mutually exclusive because they share the same IC pins (please refer to the pinout to identify the exclusions). The two main types of operation are host controlled and stand-alone. There are three main possible ways of communication with a host processor: * * * 8-bit parallel MPU type bi-directional interface signals: D7 - D0, CS, WR, RD, A0, IRQ Asynchronous serial, MIDI_IN and, optionally, MIDI_OUT Synchronous serial signals: SDIN, SCLK, SYNC, INT
The MPU type interface allows downloading firmware to the chip from the host. If another interface is used, then external EEPROM or DataFlash is required. Stand-alone Operation Possible stand-alone modes are: * * Firmware into external ROM or DataFlash Firmware into external SmartMedia. In this case, the firmware should reside in the SmartMedia reserved sectors starting at sector #1.
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Pinout
Pin Description
* * * Table 2. Pinout by Pin Name
Pin Name GND VC18 VC33 PWRIN PWROUT D7 - D0 I/O7 - I/O0 P0.7 - P0.0 CLAD3 - 0 Pin Number 4, 13, 19, 25 , 36, 43, 48, 57 12, 31, 46, 63 3, 32 18 17 59, 58, 56, 55, 52, 51, 50, 49 59, 58, 56, 55, 52, 51, 50, 49 59, 58, 56, 55, 52, 51, 50, 49 59, 58, 56, 55 Type PWR PWR PWR PWR PWR I/O I/O I/O In Sharing Description 1 1 1 1 Digital ground. All these pins should be returned to a ground plane Core power. All these pins should be returned to nominal 1.8V or to PWROUT if the built-in power switch is used. Periphery power. All these pins should be returned to nominal 3.3V. Power switch input; should be returned to nominal 1.8V even if the power switch is not used Power switch output; should be connected to all VC18 pins if the power switch is used Slave 8-bit interface data. Output if CS and RD are low (read from chip), input if CS and WR are low (write to chip). Type of data defined by A0 input. SmartMedia data or other peripheral data General-purpose I/O; can be programmed individually as input or output Optional bit clocks for digital audio input. Used for sampling rate conversion, for external incoming digital audio such as AES/BEU or S/Pdif. Optional word selects for digital audio input. Used for sampling rate conversion, for external incoming digital audio such as AES/BEU or S/Pdif. Slave 8-bit interface address. Indicates data/status or data/ctrl transfer type (CS RD low or CS WR low) SmartMedia presence detect General-purpose input pin Serial slave synchronous interface input clock Slave 8-bit interface chip select, active low General-purpose input pin Serial slave synchronous interface input sync signal Slave 8-bit interface write, active low. D7 - D0 data is sampled by chip on WR rising edge if CS is low SmartMedia configuration. This pin is sensed after power-up. If found low, it is assumed that a SmartMedia connector is present. The built-in firmware will wait for SmartMedia SMPD. General-purpose input pin Slave 8-bit interface read, active low. D7 - D0 data is output when RD goes low and CS is low
Identical sharing number indicates multifunction pins. Pd indicates a pin with built-in pull-down resistor. Pu indicates a pin with built-in pull-up resistor.
WSAD3 - 0
52, 51, 50, 49
In
1
A0 SMPD P0.10 SCLK CS P0.11 SYNC WR SMC
60 60 60 60 64 64 64 1 1
In In In In In In In In In
2 2 2 2 3 3 3 4 4
P0.12 RD
1 2
In In
4 5
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Table 2. Pinout by Pin Name (Continued)
Pin Name R|B P0.13 IRQ SMRE FS0 P0.8 INT MIDI_IN P0.14 SDIN MIDI_OUT FS1 Pin Number 2 2 8 8 8 8 8 9 9 9 10 10 Type In In Out Out In I/O Out In In In Out In Sharing Description 5 5 6 6 6 6 6 7 7 7 8 8 SmartMedia Ready Busy/ status General-purpose input pin Slave 8-bit interface interrupt request. High when data is ready to be transferred from chip to host. Reset by a read from host (CS = 0 and RD = 0) SmartMedia read enable (RE), active low Freq sense, sensed at power up. Together with FS1, allows the firmware to know the operating freq of the chip (see FS1). General-purpose I/O pin Serial slave synchronous interface data request, active low Serial MIDI in General-purpose input pin Serial slave synchronous interface input data Serial MIDI out Freq sense, sensed at power up. FS1/FS0 allow firmware to know operating frequency of chip as follows: 00 6.9552 MHz 01 9.6 MHz 10 11.2896 MHz 11 12.288 MHz General-purpose I/O Four stereo channels of digital audio output, I2S format Audio bit clock for DABD3 - 0. Audio bit clock for DAAD3 - 0 if the corresponding CLAD3 - 0 is not used. Audio left/right channel select for DABD3 - 0. Audio left/right channel for DAAD3 - 0 if the corresponding WSAD3 - 0 is not used. External DAC/Codec master clock. Same frequency as X2 pin. Can be programmed to be 128 x Fs, 192 x Fs, 256 x Fs, 384 x Fs, where Fs is the DAC/Codec sampling rate. Stereo audio data input, I2S format. Can operate on CLBD master rate or CLAD0 external rate when sampling rate conversion is requested. General-purpose input pin Three additional channels of stereo audio input, I2S format. Can individually operate on CLBD master rate or corresponding CLAD3 - 1 when sampling rate conversion is requested. DAAD3 - 1 have built-in pull-downs. They may be left open if not used. External DAC/Codec Mute. Sensed at power up. If found high, then MUTE becomes an active high output. If found low, then MUTE becomes an active low output. General-purpose I/O pin SmartMedia chip enable (CE), active low General-purpose I/O pin SmartMedia address latch enable (ALE)
P0.9 DABD3 - 0 CLBD WSBD CKOUT
10 42, 41, 40, 39 6 7 5
I/O Out Out Out Out
8 -
DAAD0 P0.15 DAAD3 - 1
34 34 38, 37 35
In In In Pd
9 9 -
MUTE
11
I/O
10
P1.6 SMCE P1.5 SMALE
11 29 29 28
I/O Out I/O Out
10 11 11 12
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Table 2. Pinout by Pin Name (Continued)
Pin Name P1.4 SMWE P1.3 SMCLE P1.2 DFCS DFSI DFSO DFSCK P1.15 - P1.11 X1 - X2 Pin Number 28 27 27 26 26 14 16 21 15 30, 62, 61, 54, 53 45, 44 Type I/O Out I/O Out I/O Out Out In Pd Out I/O Pu Sharing Description 12 13 13 14 14 General-purpose I/O pin SmartMedia write enable (WE), active low General-purpose I/O pin SmartMedia command latch enable (CLE) General-purpose I/O pin DataFlash chip select DataFlash serial input (to DataFlash) DataFlash serial output (from DataFlash). This pin has a built-in pulldown. It may be left open if not used. DataFlash data clock Five General-purpose I/O pins. These pins have built-in pull-ups. They may be left open if not used. External crystal connection. Standard frequencies are 6.9552 MHz, 9.6 MHz, 11.2896 MHz, 12.288 MHz. Max frequency is 12.5 MHz. An external clock (max. 1.8VPP) can be connected to X1 using AC coupling (22 pF). A built-in PLL multiplies the clock frequency by 4 for internal use. PLL decoupling RCR filter Master reset Schmitt trigger input, active low. RESET should be held low during at least 10 ms after power is applied. On the rising edge of RESET, the chip enters an initialization routine, which may involve firmware download from an external SmartMedia, DataFlash or host. Serial test input. This is a 57.6 Kbaud asynchronous input used for firmware debugging. This pin is tested at power-up. The built-in debugger starts if STIN is found high. STIN has a built-in pull-down. It should be grounded or left open for normal operation. Serial test output. 57.6 Kbaud async output used for firmware debugging. Power down input, active low. High level on this pin is typ. VC18. When PDWN is low, the oscillator and PLL are stopped, the power switch opens, and the chip enters a deep sleep mode (1 A typ. consumption when power switch is used). To exit from power down, PDWN has to be set high then RESET applied. Alternate programmable power-downs are available which allow warm restart of the chip. Test input. Should be grounded or left open.
LFT RESET
47 22
In
-
STIN
23
In Pd
-
STOUT PDWN
24 20
Out In
-
TEST
33
In Pd
-
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Pinout by Pin Number
Table 3. ATSAM3133 Pinout by Pin Number
Pin # Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 WR SMC P0.12 RD R|B P0.13 VC33 GND CKOUT CLBD WSBD IRQ SMRE FS0 P0.8 MIDI_IN P0.14 SDIN MIDI_OUT FS1 P0.9 MUTE P1.6 VC18 GND DFCS DFSCK DFSI Pin # Pin Name 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PWROUT PWRIN GND PDWN DFSO RESET STIN STOUT GND SMCLE P1.2 SMWE P1.3 SMALE P1.4 SMCE P1.5 P1.15 VC18 VC33 Pin # Pin Name 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 TEST DAAD0 P0.15 DAAD1 GND DAAD2 DAAD3 DABD0 DABD1 DABD2 DABD3 GND X2 X1 VC18 LFT GND Pin # Pin Name 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 D0 I/O0 P0.0 WSAD0 D1 I/O1 P0.1 WSAD1 D2 I/O2 P0.2 WSAD2 D3 I/O3 P0.3 WSAD3 P1.11 P1.12 D4 I/O4 P0.4 CLAD0 D5 I/O5 P0.5 CLAD1 GND D6 I/O6 P0.7 CLAD2 D7 I/O7 P0.7 CLAD3 A0 SMPD P0.10 SCLK P1.13 P1.14 VC18 CS P0.11 SYNC
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Mechanical Dimensions
Figure 7. Thin Plastic 64-lead Quad Flat Pack (TQFP64)
Table 4. Package Dimensions in mm
Denomination A A1 A2 L D D1 E E1 P B 0.17 Min 1.40 0.05 1.35 0.45 Nom 1.50 0.10 1.40 0.60 12.00 10.00 12.00 10.00 0.50 0.22 0.27 Max 1.60 0.15 1.45 0.75
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Electrical Characteristics
Absolute Maximum Ratings(*)
Ambient Temperature (power applied)................-40C to 85C Storage Temperature ........................................-65C to 150C Voltage on any pin X1, LFT ....................................................... -0.3 to VC18 + 0.3V Others ......................................................... -0.3 to VC33 + 0.3V Supply Voltage.......................................................................... VC18 .................................................................... -0.3V to 1.95V VC3 .......................................................................-0.3V to 3.6V Maximum IOL per I/O pin................................................. 4 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Table 5. Recommended Operating Conditions
Symbol VC18 VC33 PWRIN TA Note: Parameter Supply voltage Supply voltage
(1)
Min 1.65 3 1.75 0
Typ 1.8 3.3 1.9 -
Max 1.95 VC18 + 1.5 3.6 1.95 70
Unit V V V C
Supply voltage PWRIN pin Operating ambient temperature
1. Operation at lower VC33 values down to VC18 is possible, however external timing may be impaired. Please contact Atmel in case of use of these circuits with VC33 outside the recommended operating range.
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DC Characteristics
Table 6. DC Characteristics (TA = 25C, VC18 = 1.8V 10%, VC33 = 3.3V 10%)
Symbol VIL VIH VIH VOL VOH ICC1 ICC2 ICC3 Parameter Low level input voltage High level input voltage, except X1, PDWN High level input voltage X1, PDWN Low level output voltage IOL = -2 mA High level output voltage IOH = 2 mA VC18 power supply current (crystal freq. = 11.2896 MHz, all three P24s running) VC18 power supply current (crystal freq. = 11.2896 MHz, all P24s stopped) VC18 power supply current (crystal freq. = 11.2896 MHz, all P24s stopped, warm start power-down active) VC18 deep power down supply current (using power switch) Built-in pull-up/pull-down resistor Min -0.3 2.3 1.2 2.9 Typ 40 22 4 Max 1.0 VC33 + 0.3 VC18 + 0.3 0.4 Unit V V V V V mA mA mA
ICC4 PU/PD
10
1 -
10 56
A k
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Peripherals and Timings
Slave 8-bit Parallel Interface
Timings Pins used: D7-D0 (I/O), CS (input), A0 (input), WR (input), RD (input), IRQ (output). This interface is typically used to connect the chip to a host processor. Figure 8. Host Interface Read Cycle
A0 tAVCS CS
tCSLRDL RD
tPRD
tRDHCSH
tRDLDV D0 - D7
tDRH
Figure 9. Host Interface Write Cycle
A0 tAVCS CS
tCSLWRL WR
tPWR
tWRHCSH
tDWS D0 - D7
tDWH
Table 7. Timing Parameters
Symbol tAVCS tCSLRDL tRDHCSH tPRD tRDLDV tDRH tCSLRWRL tWRHCSH tPWR tDWS tDWH Parameter Address valid to chip select low Chip select low to RD low RD high to CS high RD pulse width Data out valid from RD Data out hold from RD Chip select low to WR low WR high to CS high WR pulse width Write data setup time Write data hold time Min 0 5 5 50 5 5 5 50 10 0 Typ Max 20 10 Unit ns ns ns ns ns ns ns ns ns ns ns
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IO Status Register
7 TE 6 RF 5 X 4 X 3 X 2 X 1 X 0 X
Status register is read when A0 = 1, RD = 0, CS = 0. * TE: Transmit Empty If 0, data from ATSAM3103 to host is pending and IRQ is high. Reading the data at A0 = 0 will set TE to 1 and clear IRQ. * RF: Receiver Full If 0, then ATSAM3103 is ready to accept DATA from host.
Note: If status bit RF is not checked by host, write cycle time should not be lower than 3 s.
SmartMedia and Other Peripheral Interfaces
This is a master 8-bit parallel interface that provides connection to SmartMedia or other peripherals such as LCD screens. Pins used: I/O7 - I/O0 (I/O), SMPD (input), SMCE, SMALE, SMCLE, SMRE, SMWE (outputs) All these pins are fully under firmware control, therefore timing compatibility is ensured by firmware only.
EEPROM/DataFlash Interface
This is a master synchronous serial interface, operating in SPI mode 0. Pins used: DFCS, DFSI, DFSCK (outputs), DFSO (input) The DFSCK frequency is firmware programmable from fck to fck/64, where fck is the crystal frequency. Thus a large variety of EEPROM/DataFlash devices can be accomodated. Please refer to Atmel DataFlash datasheets for accurate SPI mode 0 timing. Figure 10. Typical DataFlash Interface Timing
DFSCK
DFSI
LSB
DFSO
MSB
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Serial Slave Synchronous Interface
The ATSAM3103 can be controlled by an external host processor through the unidirectional serial interface. However, no firmware can be downloaded at power-up through this interface. Therefore an external ROM/Flash/EEPROM is required. Pins used: SCLK, SYNC, SDIN (input), INT (output) Data is shifted MSB first. The IC samples an incoming SDIN bit on the rising edge of SCLK, therefore the host should change SDIN on the negative SCLK edge. SYNC allows initial synchronization. The rising edge of SYNC, which should occur with SCLK low, indicates that SDIN will hold MSB data on the next rising SCLK. The data is stored internally in a 256-byte FIFO. When the FIFO count is below 64, the INT output goes low. This allows the host processor to send data in burst mode. The maximum SCLK frequency is fck (fck being the crystal frequency). The minimum time between two bytes is 64 fck periods. The contents of the SDIN data are defined by the firmware. Figure 11. Serial Slave Interface Typical Timing
SCLK
SYNC
SDIN
MSB
Digital Audio
Pins used: CLBD (output), WSBD (output), DABD3 - 0 (outputs), DAAD3 - 0 (inputs) Optionally: CLAD3 - 0 (inputs), WSAD3 - 0 (inputs) The ATSAM3103 allows for 8 digital audio output channels and 8 digital audio input channels. All audio channels are normally synchronized on single clocks CLBD, WSBD which are derived from the IC crystal oscillator. However, as a firmware option, the DAAD3 - 0 inputs can be synchronized with incoming CLAD3 - 0 and WSAD3 - 0 signals. In this case, the incoming sampling frequencies must be lower or equal to the chip sampling frequency. The digital audio timing follows the I2S standard, with up to 24 bits per sample
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Figure 12. Digital Audio
tCW WSBD tCW tCLBD
CLBD tSOD DABD3 - 0 DAAD3 - 0 tSOD
Table 8. Digital Audio Timing Parameters
Symbol tCW tSOD tCLBD Parameter CLBD rising to WSBD change DABD valid prior/after CLBD rising CLBD cycle time Min tC - 10 tC - 10 Typ 2 * tC Max Unit ns ns ns
tC is related to tCK, the crystal period at X1 as follows: Table 9. Sample Frequency
Sample Frequency WSBD 1/(tCK * 128) 1/(tCK * 192) 1/(tCK * 256) 1/(tCK * 384) Typical Sample Frequency 96 kHz 64 kHz 48 kHz 32 kHz tC tCK 2 * tCK 2 * tCK 4 * tCK CLBD/WSBD Frequency Ratio 64 48 64 48
The choice of sample frequency is done by the firmware. Figure 13. Digital Audio Frame Format, 128 x Fs and 256 x Fs Modes
WSBD
CLBD
DABD3 - 0 DAAD3 - 0 MSB LSB 16 bits LSB 24 bits MSB
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Figure 14. Digital Audio Frame Format, 192 x Fs and 384 x Fs Modes
WSBD
CLBD
DABD3 - 0 DAAD3 - 0 MSB LSB 16 bits LSB MSB 24 bits
Serial MIDI_IN and MIDI_OUT
The serial MIDI IN and OUT signals are asynchronous signals following the MIDI transmission standard: * * Baud rate: 31.25 kHz Format: start, 8 data bits, 1 stop
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Reset and Power-down
During power-up, the RESET input should be held low until the crystal oscillator and PLL are stabilized, which takes max. 10 ms. After the low-to-high transition of RESET, the following occurs: * * * * All P24s enter an idle state. P16 program execution starts in built-in ROM. STIN is sensed. If HIGH, then the built-in debugger is started. SMC is sensed. If LOW, then the built-in loader waits for SmartMedia presence detect (SMPD). When detected, the firmware is downloaded from SmartMedia reserved sector 1 and started. An attempt is made to read the first two bytes of an external EEPROM or DataFlash. If "DR" is read, then the built-in loader loads the firmware from the external EEPROM/DataFlash and starts it. Firmware download from a host processor is assumed.
The power-up sequence is as follows:
*
*
1. The byte 0ACh is written to the host, this raises IRQ. The host can recognize that the chip is ready to accept program download. Higher speed transfer can be reached by polling the parallel interface status (CS = 0, A0 = 1, RD = 0). 2. The host sends the firmware size (in words) on two bytes (Low byte first). 3. The host sends the ATSAM3103 firmware. The firmware should begin with string "DR". 4. The byte 0ACh is written to the host, this raises IRQ. The host recognizes that the chip has accepted the firmware. 5. ATSAM3103 starts the firmware. If PDWN is asserted low, then the crystal oscillator and PLL are stopped. If the power switch is used, then the chip enters a deep power-down sleep mode, as power is removed from the core. To exit power down, PDWN has to be asserted high, then RESET applied. Other power reduction features allowing warm restart are controlled by firmware: * * P24s can be individually stopped. The clock frequency can be internally divided by 256.
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Recommended Board Layout
Like all HCMOS high integration ICs, the following simple rules of board layout are mandatory for reliable operation: * GND, VC33, VC18 Distribution and Decouplings All GND, VC33, VC18 pins should be connected. A GND plane is strongly recommended. The board GND + VC33 distribution should be in grid form. Recommended VC18 decoupling is 0.1 F at each corner of the IC with an additional 10 F decoupling close to the crystal. VC33 requires a single 0.1F decoupling. * Crystal, LFT The paths between the crystal, the crystal compensation capacitors, the LFT filter R-CR and the ATSAM3103 should be short and shielded. The ground return from the compensation capacitors and LFT filter should be the GND plane from ATSAM3103. * Buses A ground plane should be implemented below the D0 - D7 bus, which is connected to the host and to the ATSAM3103 GND. A ground plane should be implemented below the WA0 - WA21/WD0 - WD15 bus, which is connected to the ROM/Flash grounds and to the ATSAM3103. * Analog Section A specific AGND ground plane should be provided, which is connected to the GND ground by a single trace. No digital signals should cross the AGND plane. Refer to the Codec vendor recommended layout for correct implementation of the analog section.
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Recommended Crystal Compensation and LFT Filter
Figure 15. Recommended Crystal Compensation and LFT Filter
X1 X1 X2 LFT
22 pF 22 pF 10 nF 1 nF
560
GND
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Product Development and Debugging
Atmel provides an integrated product development and debugging tool SamVS. SamVS runs under Windows(R) (98, ME, 2000, XP). Within the environment, it is possible to: * * * * Edit Assemble Debug on real target (In-circuit Emulation) Program Dataflash, EEPROM, SmartMedia on target.
Two dedicated IC pins, STIN and STOUT allow running firmware directly into the target using standard PC COM port communication at 57.6 Kbauds. Thus time-to-market is optimized by testing directly on the final prototype. A library of frequently used functions is available, such as: * * * * Reverb/Chorus MP3 decode 31-band equalizer Parametric equalizer
Atmel engineers are available to study customer-specific applications.
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Document Details
Title Literature Number ATSAM3103 6093
Revision History
Version A Publication Date: 25-Oct-04
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Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
(c) Atmel Corporation 2004. All rights reserved. Atmel (R) , logo and combinations thereof, Dream (R) and DataFlash(R) are registered trademarks, and Everywhere You Are SM is the trademark of of Atmel Corporation or its subsidiaries. Windows(R) 98, Windows(R) 2000, Windows(R) ME and Windows(R) XP are the registered trademarks of Microsoft Corporation. SmartMediaTM is the trademark of SanDisk Corp. MPEG Layer-3 audio decoding technology licensed from Fraunhofer IIS and Thomson Multimedia. Other terms and product names may be the trademarks of others. Printed on recycled paper.
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